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w536q020/q030/q060/q090/q120 voice/melody/lcd controller (viewtalk tm series) publication release date: may 20, 2003 - 1 - revision a2 table of contents- 1. general des cription ......................................................................................................... 2 2. features ....................................................................................................................... .......... 3 3. block di agram .................................................................................................................. .... 5 4. pad descri ption ................................................................................................................... 6 5. electrical chara cteristics ........................................................................................... 9 5.1 absolute maxi mum rati ngs ............................................................................................... 9 5.2 dc characte ristics ............................................................................................................. 9 5.3 ac characte ristics ........................................................................................................... 11 6. typical application circui ts ........................................................................................ 14 6.1 sub clock with rc m ode ................................................................................................. 14 6.2 sub clock with crystal mode ........................................................................................... 15 7. revision history ............................................................................................................... .16
w536q020/q030/q060/q090/q120 - 2 - 1. general description the w536qxxx, a member of viewtalk tm family, is a high-performance 4-bit micro-controller (uc) with built-in speech unit, melody unit and 40seg * 16 com lcd driver unit which includes internal regulator pump circuit and dedicated one pages lcd ra m. the 4-bit uc core contains dual clock source, 4-bit alu, two 8-bit time rs, one 14 bits divider, 12 pads for input or output, 7 interrupt sources and 8-level nesting for subroutine/interrupt applications . speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4k sample rate with 5 bits mdpcm), is capable of expanding to 512 seconds speech addressed by external memory w55xxx with serial bus interface. it can be implemented with winbond power speech usi ng mdpcm algorithm. melody unit provides dual tone output and can store up to 1k notes. power r eduction mode is also built in to minimize power dissipation. it is ideal for games, educational to ys, remote controllers, watches, clocks and other application products that incorpor ate both lcd display and speech. part no w536q020 W536Q030 w536q060 w536q090 w536q120 voice 20 sec 30 sec 60 sec 90 sec 120 sec i/o pad 8i/o, 4i (ra/rb/rd) 8i/o, 4i (ra/rb/rd) 8i/o, 8i (ra/rb/rc/rd) 8i/o, 8i, 8o (ra/rb/rc/rd/ re/rf) 8i/o, 8i, 8o (ra/rb/rc/rd/ re/rf) wdt disable/enable (mask option) y y y y y sub-clock rc/xtal mode (mask option) y y y y y rd port shared as serial bus (mask option) y(1) y(1) y(1) n n tri-state serial bus (mask option) (3) y y y n n cascaded voice rom through serial bus (2) n n y(1) n y notes: 1. share 3 pads of rd port (rd1/addr, rd2/data and rd3/clk) 2. dedicate serial bus 3 pads (addr, data and clk) to interface with w55xxx. cascaded voice rom can help to expand voice up to 512 sec by w55xxx chip. 3. tri-state serial bus mask option can float serial bus while voice playing is no active. let this mask option is disabled to get minimum power consumption in general.
w536q020/q030/q060/q090/q120 publication release date: may 20, 2003 - 3 - revision a2 2. features ? operating voltage: 2.4 volt ~ 5.5 volt ? watch dog disabled/enabled by mask option ? dual clock operating system ? main clock with ring/crystal (400 khz to 4 mhz) ? sub-clock with 32.768 khz rc/crystal by mask option ? memory ? program rom (p-rom): 16k 20 (rom bank0) ? data ram (w-ram): 1k 4 bit (ram bank 0 is 512 nibbles from 0:000~ 0:1ff and 0:380~0:3ff are mapped to special register. ram bank f is 512 nibbles from f: 200~f: 3ff either data ram or dedicated to script kernel) ? lcd ram (l-ram): 160 4 bit 1 pages (ram bank1 from 260~2ff) ? maximum 24 input/output pads ? ports for input only: 8 pads (rc, rd port; rd1~3 can share as serial bus for external memory w55xxx interface @w536q020/q030/q060) ? ports for output only: 8 pads (re & rf port; w536q090/q120 available only) ? ports for input/output: 8 pads (ra and rb port) ? power-down mode ? hold mode (except for 32khz oscillator) ? stop mode (including 32khz oscillator and release by rd or rc port) ? seven types of interrupts ? five internal interrupts (divider, timer 0, timer 1, speech, melody) ? two external interrupts (rd, ra) ? one built-in 14-bit clock frequency divider circuit ? two built-in 8-bit programmable countdown timers ? timer 0: one of two clock sources (fosc/4 or fosc/1024) can be selected ? timer 1: built-in auto-reload function includes internal timer ? built-in 18/14-bit watchdog timer for system reset. ? powerful instruction sets ? 8-level subroutine (including interrupt) nesting ? lcd driver unit capability ? vlcd higher than (v dd -0.5v) ? built-in voltage regulator to v2 pad ? 40 seg 16 com (seg: 24~63; com: 0~15) ? 1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register ? com 8~15 and seg40~63 can be shared as general input/output by special register ? either uc rom or voice rom used as lcd picture
w536q020/q030/q060/q090/q120 - 4 - speech function provided 640k/ 1m/ 2m/ 3m/ 4m bits voice rom for w536q020/ q030/ q060/ q090/ q120 based on 5 bits mdpcm algorithm voice rom (v-rom) available for uc data or lcd picture data. maximum 8*256 label/interrupt vector (voice section number) available provide two types of speech busy flag to either each go or each trigger maximum up to 16m bits speech address capability interface with external memory w55xxx through serial bus. x melody function provide 1k notes (22bits/ note) dedicated melody rom provide two types of melody busy flag to uc either each note or each song provide 6 kinds of beat, 16 kinds of tempo, and pitch range from g3# to c7 tremolo, triple frequency and 3 kinds of percussion available maximum 31 songs available x can mix speech with melody x multi-engine controller x direct driving speaker /buzzer or dac output x chip on board available
w536q020/q030/q060/q090/q120 publ i c at i on rel e ase dat e : may 20, 2003 - 5 - revi si on a2 3. block diagram xin xout x32i x32o lcd driver pc stack (8 levels) timer 0 timer 1 watch dog alu acc divide rom 16k*20bit ram 1k*4bit special register hcf hef ief evf flag1 psr0 mr0 pef flag0 lpx3 pm0 lpx2 lpx0 lpx1 vlcd pump & regulator lpx4 lpx5 lpy0 lpy1 spc mld dual tone melody (1k notes) mld_play mld_busy speech mdpcm core spc_play spc_busy interrupt ,hold & stop control voice rom (640k/1mbits) lpxy shared_rom data seg24~63 v3,v4,v5,v6 dh1,dh2 com0~15 v2 timing generator vdd vss res pwm1/dac rosc vssp test pwm/dac mix block pwm2 vddp port ra tone ra0~3 port rd rd0~3 port rb rb0~3 port rc rc0~3 port rf rf0~3 port re re0~3 wrp rdp spdata parallel to serial
w536q020/q030/q060/q090/q120 - 6 - 3 4. pad description s y m b o l i / o function x i n / r x i n i input pad for main clock oscillator. it can be connected to crystal when crystal mode is selected (scr0.2=1), otherwise connect a resistor to vdd to generate main system cl ock while ring mode is selected (scr0.2=0 and default). oscillator can be enabled or stopped by set scr0.1 to 1 or clear to 0 separatel y. external capacitor connects to start oscillation and get more accurate clock when while crystal mode x o u t o output pad for oscillator that is connected to another crystal pad when in crystal mode. external capacitor connects to start oscillation when in crystal mode. x 3 2 i / r s u b 1 i 32.768 khz crystal input pad or external resistor node 1 by mask option . external 15~20pf capacitor connects to start oscillation and get more accurate clock when in crystal mode. x 3 2 o / r s u b 2 o 32.768 khz crystal output pad or external resistor node 2 by mask option. external 15~20pf capacitor c onnects to start oscillation and get more accurate clock when in crystal mode. ra0 ~ ra3/tone (8) i/o general input/output port specified by pm1 register. if output mode is selected, pm0 register bit 0 can be used to specify cmos/nmos driving capability option (7). initia l state is input mode. ra3 may be uses as tone if bit 0 of mr0 specia l register is set to logic 1. an interrupt source. rb0 ~ rb3 (8) i/o general input/output port specified by pm2 register. if output mode is selected, pm0 register bit 1 can be used to specify cmos/nmos driving capability option (7). in itial state is input mode. rc0 ~ rc3 i 4-bit schmitter input with internal pull high option specified by pm3 register bit 2. each pad has an independent interrupt capability specified by pefl special register. interrupt and stop mode wake up source. rc0 is also the external event counter source of timer1. rd0 rd1/addr rd2/data rd3/clk (4) i 4-bit schmitter input port with internal pull high option specified by pm3 register bit 3. each pad has an independent interrupt capability specified by pefh special register. interrupt and stop mode wake up source. rd1~3 will be shared as the external memory w55xxx interface pads while rd port shared as serial bus mask option is enabled. "tri-state serial bus" mask option can use to float clk/addr/spdatd while "rd port shared as serial bus" mask option is enabled. re0~re3 (8) o output port only. pm3 register bit 0 can be used to specify cmos/nmos driving capability option. (w536q090/q120 only) rf0~rf3 (8) o output port only. pm3 register bit 1 can be used to specify cmos/nmos driving capability option. (w536q090/q120 only) res i system reset pad, active low with internal pull-high resistor. test i test pad. active high with internal pull low resistor.
w536q020/q030/q060/q090/q120 publication release date: may 20, 2003 - 7 - revision a2 pad description, continued symbol i/o function rosc i connect resistor to v dd pad to generate speech or melody playing clock source. pwm1/dac o while speech or melody is active, pw m1/dac is speaker direct driving output or dac output contro lled by voice output file. pwm2 o while speech or melody is active , pwm2 is another speaker direct driving output. addr (5) o external serial memory address write clock for voice extension (w536q120 only). clk (5) o external serial memory address read clock for voice extension. (w536q120 only). data (5) i/o external serial memory data in /out for voice extension (w536q120 only). seg24? seg39 o dedicated lcd segment output pads. seg40/portn.0 ? seg43/portn.3 o/o lcd segment output pads, and can be shared as general output by register lcdm3 bit 1. default function is segment pad. seg44/portm.0 ? seg47/portm.3 o/i lcd segment output pads, and can be shared as general input by register lcdm3 bit 0. default f unction is segment pad and pm5.1=0 to inhibit lcd waveform abnormal. seg48/portl.0 ? seg51/portl.3 o/o lcd segment output pads, and can be shared as general output by register lcdm2 bit 3. default function is segment pad. seg52/portk.0 ? seg55/portk.3 o/i lcd segment output pads, and can be shared as general input by register lcdm2 bit 2. default func tion is segment pad and pm5.0 = 0 to inhibit lcd waveform abnormal. seg56/portj.0 ? seg59/portj.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 1. pm4 register is used to select input or output while shared i/o function is active . default function is segment pad and pm4.3 = 0 to inhibit lcd waveform abnormal. seg60/porti.0 ? seg63/porti.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 0. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.2 = 0 to inhibit lcd waveform abnormal.
w536q020/q030/q060/q090/q120 - 8 - pad description, continued symbol i/o function com0 com7 o lcd common signal output pads either 1/16 duty or 1/8 duty. the lcd frame rate is controlled by lcdm1 register, and default value lcdm1 = 0111b with 64hz frame rate. com8 / portp.0 ~ com11/portp.3 o/o lcd common signal output pads, or shared as general output by register lcdm3.2 when in 1/8 duty mode. default function is common function. com12/porto.0 ~ com15/porto.3 o/i lcd common signal output pads, or shared as general input by register lcdm3.2 when in 1/8 duty mode. default function is common function and pm5.2 = 0 to inhibit lcd waveform abnormal. dh1, dh2 (6) o connection terminal for voltage double capacitor with 0.1uf. the dh2 connects to capacitor positive node and dh1 negative node if polar capacitor is used. v3 ~ v6 (6) o lcd com/seg output driving vo ltage. need an external 0.1uf capacitor to every pad terminal. v2 (6) i/o voltage regulator output pad. an exter nal capacitor is a must. output level can be controlled from 0~fh by lcdm4 register. if internal pump is enabled (lcdm3.3 = 0 and default value), lcd operating voltage (vlcd) will be 4*v2 or 5*v2 depending on 1/4 bias or 1/5 bias. a limitation should be noted that vlcd must be higher than (v dd -0.5v) to avoid chip leakage current. while external reference voltage is selected (lcdm3.3 = 1), v2 pad input voltage cannot be over 1.5 volt to inhibit chip damage. v ssp (7) i power ground for pwm or dac playing output. v ss (7) i power ground v ddp (7) i power source for pwm or dac playing output. v dd (7) i power source. notes: (4) rd1~3 are shared as addr/data/clk to interface with w55xxx (5) w536q120 only (6) 0.1uf is default value, and capacitor value should be larger than 0.1uf if lcd dot size over 0.5mm * 0.5mm. (7) external application circ uit should connect together, pleas e refer to application circuit. to sure chip operation properly, please bond all v dd , v ddp , v ss and v ssp pads and connect v ss and v ssp from chip outside pcb circuit. (8) when working at nmos open drain mode, external pull high voltage can't higher than vdd to avoid leakage current.
w536q020/q030/q060/q090/q120 publication release date: may 20, 2003 - 9 - revision a2 5. electrical characteristics 5.1 absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 5.2 dc characteristics (v dd ? v ss = 3.0v, no load, fm = 4 mhz with ring mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd panel on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min typ max unit op. voltage v dd 2.4 5.5 v dual clock with crystal - 600 700 a dual clock with rc type 600 700 sub-clock only, lcd off 40 50 op. current (no load, no voice, no melody) i op1 sub-clock only, lcd on 70 90 hold mode current (no load, lcd off) i op2 sub-clock active only 6 10 a hold mode current (no load, lcd on) i op3 sub-clock active only 70 a stop mode current i op4 lcd auto off 1 a addr/clk output high current io h1 vout = 2.7v -0.8 ma addr/clk output low current io l1 vout = 0.4v 0.8 ma input low voltage v il - v ss - 0.3 v dd input high voltage v ih - 0.7 - 1 v dd port ra, rb, re, rf output low voltage v abl iol = 2.0 ma - - 0.4 v port ra, rb, re, rf output high voltage v abh ioh = -2.0 ma 2.4 - - v
w536q020/q030/q060/q090/q120 - 10 - dc characteristics, continued parameter sym. conditions min typ max unit ports (i, j, l, n, p) output sink current i ol3 v ol = 0.4v -300 p a pull-up resistor r d port rd 200 300 400 k : res pull-up resistor r res - 50 100 200 k : pwm1/2 source current (9) i sph volume option = 00 -20 ma (r load = 8 : between pwm1 volume option = 01 -70 and pwm2) volume option = 10 -110 volume option = 11 -135 pwm1/2 sink current (9) i spl volume option = 00 20 ma (r load = 8 : between pwm1 volume option = 01 70 and pwm2) volume option = 10 110 volume option = 11 135 dac output current i dac v dd = 3v, rl = 100ohm -4 -5 -6 ma lcd supply current i lcd no load, all seg. on - 50 - p a com/seg on resistor r on ioh = r 50 p a 5k 10k : v2 pad output voltage v rr depended on lcdm4 0.7 1.45 v v2 pad output deviation (10) v d1 no load r 5 % v2 pad voltage step v r2 lcdm4 increased 1 50 mv v6 pad output voltage (lcd's vlcd depended on v lcd 1/4 bias & no load 3.8 * v2 3.85 * v2 3.9 * v2 v lcdm4 register) (10) 1/5 bias & no load 4.75 * v2 4.8 * v2 4.85 * v2 v2 input voltage v ext lcdm3.3 = 1 1.5 v notes: (9) pwm current deviation will be r 20%. (10) deviation is governed by lcd dot size. more larger lcd dot will get larger deviation..
w536q020/q030/q060/q090/q120 publ i c at i on rel e ase dat e : may 20, 2003 - 11 - revi si on a2 5.3 ac characteristics (v dd v ss = 3.0v, no load, fm = 4 mhz w i th ring mode, fs = 32.768 khz, w i th xtal mode, t a = 25 q c, stn lcd on w i th dot size 0.5mm*0.5mm; unless otherw i se specified) parameter sym. conditions min. typ. max. unit sub-clock frequency f sub crystal type and x32in and x32o with 17pf external cap. 3 2 7 6 8 h z main-clock frequency f m rc type/crystal type 400k - 4m hz scr0.0 = 1, f sy s = f sub 3 2 7 6 8 h z chip operation frequency f os c scr0.0 = 0; f sy s = f main 4 0 0 k - 4 m i n st ruct ion cy cle time t cy c one machine cycle - 4/ f osc - s res e t ac tive width t raw fosc = 32.768 khz 1 - - p s interrupt ac tive width t iaw fosc = 32.768 khz 1 - - p s rxin = 680k : 1 m h z rxin = 330k : 2 m rxin = 200k : 3 m main clock rc frequency (11) 3 f rxin rxin = 150k : 4 m sub-clock ring oscillator f rsub r sub = 680k : 3 2 k h z sub-clock oscillation stable time @ cold start f sto p r sub = 680k : 0 . 8 1 s frequency deviation of main-clock f rxin d 2mhz ' f f f(3v) f (2.4v) f(3v ) 1 0 % frequency deviation of main-clock f rxin = 3 mhz ' f f f(3v) f (2.4v) f(3v ) 1 5 % frequency deviation of main-clock f rxin = 4 mhz ' f f f(3v) f (2.4v) f(3v ) 2 0 % rosc frequency f rosc r os c = 680k : 3 m h z frequency deviation of f rosc = 3 mhz ' f f f(3v) f (2.4v) f(3v ) 7 . 5 % frame frequency f lcd lcdm1 = 0111b(default) 6 4 h z notes: ( 11) t he deviation w ill be +20% w h ile vdd dr ops fr om 5.5v to 2.4v based on same r e sistor
w536q020/q030/q060/q090/q120 - 12 - 3 operating current vs. main clock (rc mode) iop vs. main clock rc mode 0 200 400 600 800 1000 12 34 fr e q (m hz) iop ( u a) 3v 4.5v sub-clock oscillation freq vs. resistor oscillat i on freq vs. sub- clock 33.2 20 22.5 25 27.5 30 32.5 35 37.5 40 42.5 560 620 680 750 820 1k rs ub (k ohm ) fs ub (khz) 3v 4.5v
w536q020/q030/q060/q090/q120 publ i c at i on rel e ase dat e : may 20, 2003 - 13 - revi si on a2 main-clock oscillation freq vs. resistor m a in- c lock freq vs. rxin 1.11 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 130 150 160 200 330 680 2 k r xin (k ohm) fmain (mhz) 2.4v 3v 4.5v 5.5v voice operating freq vs. resistor (rosc) voice operat ing freq. vs. r o sc 2. 25 2. 5 2. 75 3 3. 25 3. 5 3. 75 4 4. 25 470 560 680 910 ros c (k oh m ) freq (mhz) 3v 4.5v
w536q020/q030/q060/q090/q120 - 14 - 3 6. typical application circuits 6.1 sub clock w i th rc mode com0~15 seg24~63 40seg*16com lcd panel vlcd>vdd-0.5v x32io x32in r2 vddp pwm1/dac data/rd2 clk/rd3 vss vssp w536qxxx pwm2 v2 v3 v5 v6 dh2 dh1 addr/rd1 v4 speaker q1 8050 470 : c6 speaker (*3) (*1) (*4) (*5) w55mxx when 1/4 bias, v4=v5, c11 can skip vddp vddp vdd xin ___ res rosc r1 r4 c3 r5 switch c4 r3 c5 battery 1 2 c2 c1 (*2) (*4) vddp c12 c11 c10 c13 c14 c9 rd0 ra0~3 rb0~3 rc0~3 re0~3 rf0~3 component c1 c2~c4 c5, c6 c7, c8 c9~c14 r1 r2 r3 r4 v a l u e 4 . 7 u f 0.1uf 100pf 15~ 30pf 0 . 1 ~ 1 u f 6 8 0 k ? ? ? ? ? ? ?
w536q020/q030/q060/q090/q120 publ i c at i on rel e ase dat e : may 20, 2003 - 15 - revi si on a2 6.2 sub clock w i th cry s tal mode vddp pwm1/dac data/rd2 clk/rd3 vss vssp w536qxxx com0 ~7 seg24~63 pwm2 v2 v3 v5 v6 dh2 dh1 addr/rd1 v4 speaker q1 8050 470 : c6 speaker (*3) (*1) (*4) (*5) 40seg*8com lcd panel vlcd>vdd-0.5v w55mxx when 1/4 bias, v4=v5, c11 can skip vddp vddp vdd xin ___ res rosc r1 r4 c3 r5 switch c4 r3 c5 battery 1 2 c2 c1 (*2) (*4) x32io x32in 32k c7 c8 vddp c12 c11 c10 c13 c14 c9 rd0 ra0~3 rb0~3 rc0~3 re0~3 rf0~3 component c1 c2~c4 c5, c6 c7, c8 c9~c14 r1 r2 r3 r4 value 4.7uf 0 . 1 u f 1 0 0 p f 15~ 3 0 p f 0 . 1 ~ 1 u f 680k - 650k /1mhz 350k /2mhz 225k /3mhz 160k /4mhz 100 note: 1. c9~c14 depends on lcd panel dot size. 2. option r5 equals to 100 : if high noise immunity is needed. 3. for dac option application. 4. to ensure that three batteries function w e ll in w536f20 demo board. c 6 should stay close to pad pwm/pwm2 at its best. under the mask rom version, c 5 and c 6 can be skipped. 5. sure chip operation properly , please bond all v ddp , v dd , v ssp and v ss ; and connect v ssp pad to v ss from external pcb circuit. 6. main clock w i th ring ty pe, the frequency deviation is depended on v dd and resistor
w536q020/q030/q060/q090/q120 - 16 - 3 7. revision history v e r s i o n d a t e writ e r descript i o n a1 sep. 7, 2001 wtchu x establish a2 may 20, 2003 wtchu x integrate for q060/q090/q120 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. inform at i on cont ai ned i n t h i s publ i cat i on regardi ng devi ce appl i cat i ons and t h e l i k e i s i n t e nded for suggest i on only and m a y be superseded updates. no representation or warranty is given and no liability is assum e d by w i nbond electronics corp. with respect to the accuracy or use of such inform ation, or infringem e nt of patents or ot her i n t e l l ect ual propert y .

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